1. Field of the Invention
This invention relates to a digital-to-analog converting syste employed in various digital processing systems such as PCM (Pulse-Code Modulation) record players. More particularly, the invention concerns a digital-to-analog converting system, which can digital-to analog convert Pulse Amplitude Modulation (PAM) waves and Pulse Width Modulation (PWM) waves.
2. Description of the Prior art
Heretofore, digital-to-analog (D/A) converting systems, which can convert a digital signal with each bit having a fixed weight, e.g., simple binary codes and binarized decimal codes, into an analog signal, are well known in the art. These digital-to-analog converting systems include one, in which the digital signal noted above is converted to a PAM or PWM wave corresponding to digital data given by the weight of each bit and the PAM or PWM wave thus obtained is interpolated through a low-pass filter to obtain the analog signal.
With a D/A converting system which is based on a system of converting a digital signal to a PAM wave (hereinafter referred to as PAM system), principally a conversion characteristic having satisfactory linearity can be obtained. This D/A converting system, however, requires highly precise resistance adder and current adder accurately corresponding to the weight of each bit of the input digital signal. If the resolution is to be increased, therefore, increase of the circuit scale is inevitable, and also the entire circuit must be constructed with a high precision. With a D/A converting system which is based on a system of converting a digital signal to a PWM wave (hereinafter referred to as PWM system), the output pulse width may be controlled by a counter according to the input digital signal, so that the circuit construction that is required is simple. However, the conversion characteristic is principally non-linear and involves conversion errors. Also, it is necessary to increase the operation frequency of the counter according to the resolution.
FIG. 1 shows analog signals obtained through the PAM system conversion and analog signals obtained through the PWM system conversion. As is seen from the Figure, the PAM pulses and PWM pulses that are produced from digital signal by respective systems have equal areas. With the PWM pulses, with which the duty ratio with respect to the conversion period T varies, unlike the PAM pulses with which the duty ratio remains fixed, the linearity of analog signal that is obtained by smoothing the pulses through a predetermined low-pass filter is deteriorated.
More particularly, the digital-to-analog conversion characteristic of the PWM system is not linear but is gently curved as shown in FIG. 2. The non-linearity of the PWM system conversion characteristic varies according to the frequency of the analog signal obtained. The distortion due to the non-linearity is increased with increasing analog signal frequency and also with increasing maximum PWM wave pulse width in one conversion period T.
The distortion due to conversion in the PWM system noted above may be reduced by increasing the operation frequency of a counter that controls the pulse width of the PWM wave and thereby reducing the pulse width of the PWM wave representing one LSB of data. By reducing the pulse width of one LSB, however, the signal level of the analog signal that is obtained through interpolation of the PWM wave through a low-pass filter is reduced to reduce the ratio between the maximum output level and zero signal level, i.e., the dynamic range of signal.
In case where D/A conversion with a resolution of N bits is performed by the PWM system, the pulse width .tau..sub.0 representing one LSB of PWM pulses where the maximum pulse width is .tau..sub.max is given as ##EQU1## Where a 16-bit PCM audio D/A converter is employed, for instance, with a maximum pulse width .tau..sub.max of 10 .mu.sec., i.e., approximately one-half of a sampling period of 22 .mu.sec., the pulse width .tau..sub.0 representing one LSB has to be ##EQU2## In order to control the pulse width of the PWM pulses in this case with a counter, it is necessary to operate the counter at a clock frequency f.sub.CLK of ##EQU3## However, even with an ordinary high speed counter based on ECL (Emitter-Coupled Logic), the practical upper limit of the operation frequency is of the order of 100 MHz. Therefore, it has been very difficult to realize a high resolution D/A converting system based on the PWM system.
When D/A conversion with a resolution of N bits is to be realized with a PAM system employing current adders, for instance, N current sources which are provided with highly precise weights are required for each bit.